A 32-kHz-Reference 2.4-GHz Fractional-<i>N</i> Oversampling PLL With 200-kHz Loop Bandwidth

In this article, a mixed–signal, 32-kHz reference-based 2.4-GHz fractional- ${N}$ over-sampling phase-locked loop (OSPLL) is proposed. Different from the conventional notation="LaTeX">$1\times $ sampling PLL, which only uses zero-crossing timing information of reference signal, proposed OSPLL fully utilizes both voltage and domain signal realizes oversampling ratio (OSR) times phase detection (PD) in one cycle. The employs digital-to-analog converter (DAC) to construct reference-like feedback digital-to-time (DTC) improve PD resolution time domain. adaptive lookup table (LuT)-based calibration generate correct for DAC DTC control. A clocked passive comparator works as bang-bang detector (BBPD) PLL control LuTs’ construction. co-design low-noise analog circuits digital calibrations enables good jitter spur performance. fabricated 65-nm CMOS technology, with core area 0.58 mm 2 , power consumption 4.97 mW 1-V supply. It achieves 5.79-ps root-mean-square (rms) modes loop-bandwidth (BW loop ) 200 kHz, corresponding figures merit (FoMs) ?217.8 dB. measured fractional less than ?36 dBc, ?78 respectively.